1. Field of the Invention
The present invention relates to a method for extending an electrically conductive layer into an electrically insulating layer arranged on the electrically conductive layer.
2. Description of the Related Art
In recent years, semiconductor integrated circuits are being made smaller. In response to the smaller size, there is a tendency for the opening dimension of a via hole formed for connecting the multilayers of wiring to be made smaller. As a result, the diameter of the opening of the connecting portion is smaller than the depth of the via hole. Thus, it has become difficult to make connections between multilayers of wiring. A lot of improvements have been made regarding such a problem in terms of reliability. One such improvement proposed is a manufacturing method of forming a hillock on an underlayer of wiring and connecting it with an upperlayer of wiring (U.S. Pat. No. 4,728,627).
An example of a method of manufacturing semiconductor devices employing the above-mentioned conventional multilayer wiring structure will be explained below with reference to the accompanying drawings.
FIG. 20 is a cross-sectional view which illustrates conventional steps of manufacturing semiconductor devices. In FIG. 20(a), an A1-Si film having a thickness of 1.0 .mu.m is accumulated by sputtering on a semiconductor substrate 100 on which surface is formed a silicon oxide film; and the film is etched into a wiring pattern by a photolithographic process, forming a first layer of wiring 1. Thereafter, a p-SiN film 2 is accumulated to a thickness of 0.1 .mu.m, as an insulating film having the function of suppressing hillocks, on the first layer of wiring 1 by a CVD method at 300.degree. C. or lower. A p-SiN film 3 is accumulated 0.9 .mu.m at a temperature of 380.degree. C. as an interlayer insulating film. Next, a silica insulating film 4 having a thickness of 0.4 .mu.m is formed for flattening the surfaces. In FIG. 20(b), a resin pattern 5 is formed by the photolithographic process. The silica insulating film 4, the p-SiN films 3 and 2 are in turn etched by using the resin pattern 5 as a mask, thus a through hole 6 is formed in a predetermined region on the first layer of wiring 1. In FIG. 20(c), the resin pattern 5 is removed, and a hillock 7 is formed from the first layer of wiring 1 in the through hole 6 by a heat treatment step for 15 minutes at 500.degree. C. In FIG. 20(d), a second layer of wiring 8 is formed over the through hole and is connected to the first layer of wiring 1.
As a technique for forming contacts by means of which a semiconductor substrate is connected to a metallic wiring, a method has been proposed in which metallic wiring is accumulated into a contact hole and made to flow into the hole by performing heat treatment in a vacuum (the 38th Applied Physics Conference Preliminary Manuscript No. 2-31p-W-7).
An example of a method of manufacturing semiconductor devices employing the above-mentioned conventional contact forming technique will be explained below with reference to the accompanying drawings.
FIG. 21 shows cross-sectional views of conventional steps of manufacturing semiconductor devices. In FIG. 21(a), A1-Si-Cu 49A is accumulated to a thickness of 300 nm sputtering on a contact hole 48, formed on a semiconductor substrate 100, having a diameter of 0.8 .mu.m and an aspect ratio of 1. Then, heat treatment is performed at a temperature of 550.degree. C. in a vacuum, causing the A1-Si-Cu 49A to shift to the contact hole. In FIG. 21(b), the contact hole 48 is filled with the shifted A1-Si-Cu 49B.